AMD Epyc Genoa with 12 pictured chiplets
only yesterday The first image of the new SP5 (LGA6096) socket has appeared and now we can finally see the next generation EPYC processor without the built-in heat spreader.
Chiphell forum member “zhangzhonghao” appears to be the first person to reveal the true image of the upcoming Zen4 server processor, codenamed Genoa. This is the first image that shows all 12 chiplets installed on SP5.
AMD EPYC “Genoa” CPU, Source: Chiphell
EPYC Genoa features up to 96 cores and 192 series in its complete composition. AMD will release several SKUs with partially broken cores, so just because this processor has 12 chips, doesn’t mean it will have 96 active cores.
Each Zen4 CCD die has an area of 72 mm², which is 8 mm² smaller than Zen3 (such as the EPYC “Milan” series). The I/O die is also smaller, at around 397 mm² compared to 416 mm² on Zen3 EPYC CPUs. However, AMD had no problem installing 6 chips on each side of the I/O die, considering that the SP5 (LGA 6096) package is 37% larger than the SP3.
AMD 16-core EPYC Genoa processor, Source: VideoCardz
AMD’s new SP5 platform will support up to 12 channels of DDR5 memory in addition to a PCIe Gen5 interface. AMD Genoa is already shipping to early customers, according to AMD. The new EPYC 7004 series is now on its way to launch by the end of this year.
| Specifications of the rumored AMD EPYC series processors | ||||||
|---|---|---|---|---|---|---|
| Video Cards | 7001 “Naples” | 7002 “Rome” | 7003 “Milan” 7003 “Milan-X” |
7004 “Genoa” | 7004 “Bergamo” | |
| 7005 “Taurine” | launch | 2017 | 2019 | 2021 | 2022 | 2022 |
| 2023/2024 | building | 14 nm zin | 7 nm Zen 2 | 7 nm Zen 3 | 5 nm Zen4 | 5 nm Zen4c |
| Zain 5 | Plug | SP3 (LGA4094) | SP3 (LGA4094) | SP3 (LGA4094) | SP5 (LGA-6096) | SP5 (LGA-6096) |
| SP5 (LGA-6096) | Modules/slices | 4xCCD | 8xCCD + 1xIOD | 8xCCD + 1xIOD | 12xCCD + 1xIOD | 12xCCD + 1xIOD |
| TBC | ||||||
| Max cores | Max Clock | TBC | TBC | |||
| TBC | L2 cache per center | 0.5 MB | 0.5 MB | 0.5 MB | 1 megabyte | TBC |
| TBC | L3 cache per CCX | 8 MB | 8 MB | 32MB / 96MB | 32 MB | |
| TBC | ||||||
| TBC | ||||||
| memory channels | Memory support | PCIe lanes | ||||
| TBC | TBC | |||||
Max cTDP TBC source: zhangzhonghao @chevel
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